The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2010
Filed:
Sep. 21, 2007
Adam Matthew Bittner, South Burlington, VT (US);
Timothy W. Budell, Milton, VT (US);
Robert C. Cusimano, South Hero, VT (US);
Richard Dauphin, Shelburne, VT (US);
Matthew Thomas Guzowski, Essex, VT (US);
Craig Paul Lussier, Williston, VT (US);
David Brian Stone, Jericho, VT (US);
Patrick G. Wilder, Underhill, VT (US);
Adam Matthew Bittner, South Burlington, VT (US);
Timothy W. Budell, Milton, VT (US);
Robert C. Cusimano, South Hero, VT (US);
Richard Dauphin, Shelburne, VT (US);
Matthew Thomas Guzowski, Essex, VT (US);
Craig Paul Lussier, Williston, VT (US);
David Brian Stone, Jericho, VT (US);
Patrick G. Wilder, Underhill, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in a second region.