The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2010
Filed:
Jun. 23, 2005
Yen-hao Shih, Changhua, TW;
Shih-chin Lee, Siling Township, Yunlin County, TW;
Jung-yu Hsieh, Hsinchu, TW;
Erh-kun Lai, Taichung, TW;
Kuang-yeu Hsieh, Jubei, TW;
Yen-Hao Shih, Changhua, TW;
Shih-Chin Lee, Siling Township, Yunlin County, TW;
Jung-Yu Hsieh, Hsinchu, TW;
Erh-Kun Lai, Taichung, TW;
Kuang-Yeu Hsieh, Jubei, TW;
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.