The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2010

Filed:

Aug. 29, 2007
Applicants:

Wagdi W. Abadeer, Jericho, VT (US);

Jeffrey S. Brown, Middlesex, VT (US);

Kiran V. Chatty, Williston, VT (US);

Robert J. Gauthler, Jr., Hinesburg, VT (US);

Jed H. Rankin, South Burlington, VT (US);

William R. Tonti, Essex Junction, VT (US);

Inventors:

Wagdi W. Abadeer, Jericho, VT (US);

Jeffrey S. Brown, Middlesex, VT (US);

Kiran V. Chatty, Williston, VT (US);

Robert J. Gauthler, Jr., Hinesburg, VT (US);

Jed H. Rankin, South Burlington, VT (US);

William R. Tonti, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/425 (2006.01);
U.S. Cl.
CPC ...
Abstract

The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.


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