The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Sep. 26, 2007
Zhonghai Shi, Austin, TX (US);
Mark Michael, Cedar Park, TX (US);
Donna Michael, Legal Representative, Cedar Park, TX (US);
David Wu, Austin, TX (US);
James F. Buller, Austin, TX (US);
Jingrong Zhou, Austin, TX (US);
Akif Sultan, Austin, TX (US);
Zhonghai Shi, Austin, TX (US);
Mark Michael, Cedar Park, TX (US);
Donna Michael, legal representative, Cedar Park, TX (US);
David Wu, Austin, TX (US);
James F. Buller, Austin, TX (US);
Jingrong Zhou, Austin, TX (US);
Akif Sultan, Austin, TX (US);
Globalfoundries Inc., Grand Cayman, KY;
Abstract
The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.