The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Aug. 01, 2007
Venky Ramachandran, Cupertino, CA (US);
Nikhil Tripathi, Noida, IN;
Anmol Mathur, San Jose, CA (US);
Sumit Roy, San Jose, CA (US);
Malay Haldar, Noida, IN;
Venky Ramachandran, Cupertino, CA (US);
Nikhil Tripathi, Noida, IN;
Anmol Mathur, San Jose, CA (US);
Sumit Roy, San Jose, CA (US);
Malay Haldar, Noida, IN;
Calypto Design Systems, Inc., Santa Clara, CA (US);
Abstract
An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element. To this end, at least one second logic element may be disabled based on the identified condition for power savings or other purposes.