The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Sep. 05, 2007
Young-lyong Kim, Gyeonggi-do, KR;
Young-shin Choi, Chungcheongnam-do, KR;
Jong-gi Lee, Chungcheongnam-do, KR;
Kun-dae Yeom, Chungcheongnam-do, KR;
Chul-yong Jang, Busan, KR;
Hyun-jong Woo, Gyeonggi-do, KR;
Young-Lyong Kim, Gyeonggi-do, KR;
Young-Shin Choi, Chungcheongnam-do, KR;
Jong-Gi Lee, Chungcheongnam-do, KR;
Kun-Dae Yeom, Chungcheongnam-do, KR;
Chul-Yong Jang, Busan, KR;
Hyun-Jong Woo, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.