The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Oct. 31, 2007
Applicants:

Masashi Horiguchi, Kawasaki, JP;

Kunio Uchiyama, Kodaira, JP;

Kiyoo Itoh, Higashi-kurume, JP;

Takeshi Sakata, Kunitachi, JP;

Masakazu Aoki, Tokorozawa, JP;

Takayuki Kawahara, Hachioji, JP;

Inventors:

Masashi Horiguchi, Kawasaki, JP;

Kunio Uchiyama, Kodaira, JP;

Kiyoo Itoh, Higashi-kurume, JP;

Takeshi Sakata, Kunitachi, JP;

Masakazu Aoki, Tokorozawa, JP;

Takayuki Kawahara, Hachioji, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); G05F 1/10 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.


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