The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2010
Filed:
Jun. 03, 2008
Clinton Chih-chieh Chao, Hsinchu, TW;
Fei-chieh Yang, Hsin-Chu, TW;
Chun-hsing Chen, Chu-Pei, TW;
Mill-jer Wang, Hsinchu, TW;
Sheng-hsi Huang, Hsinchu, TW;
Ming-cheng Hsu, Hsin-Chu, TW;
Clinton Chih-Chieh Chao, Hsinchu, TW;
Fei-Chieh Yang, Hsin-Chu, TW;
Chun-Hsing Chen, Chu-Pei, TW;
Mill-Jer Wang, Hsinchu, TW;
Sheng-Hsi Huang, Hsinchu, TW;
Ming-Cheng Hsu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-chu, TW;
Abstract
A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.