The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2010
Filed:
Jul. 17, 2007
Scott J. Derner, Boise, ID (US);
Venkatraghavan Bringivijayaraghavan, Boise, ID (US);
Abhay S. Dixit, Boise, ID (US);
Scot M. Graham, Boise, ID (US);
Stephen R. Porter, Boise, ID (US);
Ethan A. Williford, Boise, ID (US);
Scott J. Derner, Boise, ID (US);
Venkatraghavan Bringivijayaraghavan, Boise, ID (US);
Abhay S. Dixit, Boise, ID (US);
Scot M. Graham, Boise, ID (US);
Stephen R. Porter, Boise, ID (US);
Ethan A. Williford, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.