The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2010
Filed:
Oct. 30, 2007
Tomoharu Tanaka, Yokohama, JP;
Hiroshi Nakamura, Kawasaki, JP;
Ken Takeuchi, Tokyo, JP;
Riichiro Shirota, Fujisawa, JP;
Fumitaka Arai, Kawasaki, JP;
Susumu Fujimura, Kawasaki, JP;
Tomoharu Tanaka, Yokohama, JP;
Hiroshi Nakamura, Kawasaki, JP;
Ken Takeuchi, Tokyo, JP;
Riichiro Shirota, Fujisawa, JP;
Fumitaka Arai, Kawasaki, JP;
Susumu Fujimura, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Kawasaki-shi, JP;
Abstract
A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data '0' can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.