The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2010

Filed:

Nov. 30, 2007
Applicants:

Tab A. Stephens, Buda, TX (US);

Olubunmi O. Adetutu, Austin, TX (US);

Paul A. Grudowski, Austin, TX (US);

Matthew T. Herrick, Cedar Park, TX (US);

Inventors:

Tab A. Stephens, Buda, TX (US);

Olubunmi O. Adetutu, Austin, TX (US);

Paul A. Grudowski, Austin, TX (US);

Matthew T. Herrick, Cedar Park, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.


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