The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7745239 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 29, 2010

Filed:

Jul. 14, 2006
Applicants:

O. Samuel Nakagawa, Redwood City, CA (US);

Andrew B. Kahng, Del Mar, CA (US);

Pakman Wong, Cupertino, CA (US);

Puneet Gupta, Santa Clara, CA (US);

Inventors:

O. Samuel Nakagawa, Redwood City, CA (US);

Andrew B. Kahng, Del Mar, CA (US);

Pakman Wong, Cupertino, CA (US);

Puneet Gupta, Santa Clara, CA (US);

Assignee:

Tela Innovations, Inc., Campbell, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2006.01); H01L 21/66 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit having a metal interconnect layer, and also having a conductive line and a boundary defined with a uniform distance from the conductive line that defines a 'keep out' distance between the boundary and the conductive line. A set of first fill elements are uniformly arranged along the boundary outside of the 'keep out' distance, and a set of second fill elements further from the conductive line than the first fill elements are arranged in a pattern that would be uniform, but for having some fill elements missing from the pattern.


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Nakagawa, O.. (2010). Arrangement of fill unit elements in an integrated circuit interconnect layer (U.S. Patent No. 7745239). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7745239

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