The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2010

Filed:

Jun. 03, 2008
Applicants:

Griselda Bonilla, Fishkill, NY (US);

Kaushik Chanda, Fishkill, NY (US);

Ronald G. Filippi, Wappingers Falls, NY (US);

Jeffrey P. Gambino, Westford, VT (US);

Stephan Grunow, Poughkeepsie, NY (US);

Chao-kun HU, Somers, NY (US);

Sujatha Sankaran, New Paltz, NY (US);

Andrew H. Simon, Fishkill, NY (US);

Theodorus E. Standaert, Pine Bush, NY (US);

Inventors:

Griselda Bonilla, Fishkill, NY (US);

Kaushik Chanda, Fishkill, NY (US);

Ronald G. Filippi, Wappingers Falls, NY (US);

Jeffrey P. Gambino, Westford, VT (US);

Stephan Grunow, Poughkeepsie, NY (US);

Chao-Kun Hu, Somers, NY (US);

Sujatha Sankaran, New Paltz, NY (US);

Andrew H. Simon, Fishkill, NY (US);

Theodorus E. Standaert, Pine Bush, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
Abstract

A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.


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