The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2010

Filed:

Jan. 05, 2009
Applicants:

William J. Cote, Poughquag, NY (US);

Oliver D. Patterson, Poughkeepsie, NY (US);

Inventors:

William J. Cote, Poughquag, NY (US);

Oliver D. Patterson, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.


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