The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Jul. 10, 2008
Anil Kumar Chinthakindi, Poughkeepsie, NY (US);
Douglas Duane Coolbaugh, Essex Junction, VT (US);
John Edward Florkey, Pleasant Valley, NY (US);
Jeffrey Peter Gambino, Westford, VT (US);
Zhong-xiang He, Essex Junction, VT (US);
Anthony Kendall Stamper, Williston, VT (US);
Kunal Vaed, Poughkeepsie, NY (US);
Anil Kumar Chinthakindi, Poughkeepsie, NY (US);
Douglas Duane Coolbaugh, Essex Junction, VT (US);
John Edward Florkey, Pleasant Valley, NY (US);
Jeffrey Peter Gambino, Westford, VT (US);
Zhong-Xiang He, Essex Junction, VT (US);
Anthony Kendall Stamper, Williston, VT (US);
Kunal Vaed, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.