The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2010

Filed:

Jul. 05, 2005
Applicants:

Chii-ming Wu, Taipei, TW;

Chih-wei Chang, Hsin-chu, TW;

Pang-yen Tsai, Jhu-bei, TW;

Chih-chien Chang, Yuan-Li Township, Miow-Li County, TW;

Inventors:

Chii-Ming Wu, Taipei, TW;

Chih-Wei Chang, Hsin-chu, TW;

Pang-Yen Tsai, Jhu-bei, TW;

Chih-Chien Chang, Yuan-Li Township, Miow-Li County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/366 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.


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