The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Aug. 29, 2006
Phillip Daniel Matz, Murphy, TX (US);
Sopa Chevacharoenkul, Richardson, TX (US);
Ching-te Lin, Plano, TX (US);
Basab Chatterjee, Allen, TX (US);
Anand Reddy, Dallas, TX (US);
Kenneth Joseph Newton, McKinney, TX (US);
Ju-ai Ruan, Plano, TX (US);
Phillip Daniel Matz, Murphy, TX (US);
Sopa Chevacharoenkul, Richardson, TX (US);
Ching-Te Lin, Plano, TX (US);
Basab Chatterjee, Allen, TX (US);
Anand Reddy, Dallas, TX (US);
Kenneth Joseph Newton, McKinney, TX (US);
Ju-Ai Ruan, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.