The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Oct. 24, 2005
Chih-hao Wang, Hsinchu, TW;
Yen-ping Wang, Taipei, TW;
Steve Ming Ting, Hsinchu, TW;
Yi-chun Huang, Pingjhen, TW;
Chih-Hao Wang, Hsinchu, TW;
Yen-Ping Wang, Taipei, TW;
Steve Ming Ting, Hsinchu, TW;
Yi-Chun Huang, Pingjhen, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., HsinChu, TW;
Abstract
An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.