The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Dec. 21, 2007
Kenji Sasaki, Tokyo, JP;
Ikuro Akazawa, Tokyo, JP;
Yoshinori Imamura, Tokyo, JP;
Atsushi Kurokawa, Tokyo, JP;
Tatsuhiko Ikeda, Tokyo, JP;
Hiroshi Inagawa, Tokyo, JP;
Yasunari Umemoto, Tokyo, JP;
Isao Obu, Tokyo, JP;
Kenji Sasaki, Tokyo, JP;
Ikuro Akazawa, Tokyo, JP;
Yoshinori Imamura, Tokyo, JP;
Atsushi Kurokawa, Tokyo, JP;
Tatsuhiko Ikeda, Tokyo, JP;
Hiroshi Inagawa, Tokyo, JP;
Yasunari Umemoto, Tokyo, JP;
Isao Obu, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.