The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2010
Filed:
Sep. 05, 2008
Haihong Wang, Fremont, CA (US);
Minh-van Ngo, Fremont, CA (US);
Qi Xiang, San Jose, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Eric N. Paton, Morgan Hill, CA (US);
Ming-ren Lin, Cupertino, CA (US);
Haihong Wang, Fremont, CA (US);
Minh-Van Ngo, Fremont, CA (US);
Qi Xiang, San Jose, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Eric N. Paton, Morgan Hill, CA (US);
Ming-Ren Lin, Cupertino, CA (US);
GlobalFoundries Inc., Grand Cayman, KY;
Abstract
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.