The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2010
Filed:
Dec. 18, 2007
Bruce B. Doris, Brewster, NY (US);
Kathryn W. Guarini, Yorktown Heights, NY (US);
Meikei Ieong, Wappingers Falls, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Kern Rim, Yorktown Heights, NY (US);
Jeffrey W. Sleight, Ridgefield, CT (US);
Min Yang, Yorktown Heights, NY (US);
Bruce B. Doris, Brewster, NY (US);
Kathryn W. Guarini, Yorktown Heights, NY (US);
Meikei Ieong, Wappingers Falls, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Kern Rim, Yorktown Heights, NY (US);
Jeffrey W. Sleight, Ridgefield, CT (US);
Min Yang, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.