The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2010
Filed:
Aug. 23, 2005
Yen-hao Shih, Changhua, TW;
Shih-chin Lee, Siluo Township, TW;
Jung-yu Hsieh, Hsinchu, TW;
Erh-kun Lai, Longjing Shiang, TW;
Kuang Yeu Hsieh, Jhubei, TW;
Yen-Hao Shih, Changhua, TW;
Shih-Chin Lee, Siluo Township, TW;
Jung-Yu Hsieh, Hsinchu, TW;
Erh-Kun Lai, Longjing Shiang, TW;
Kuang Yeu Hsieh, Jhubei, TW;
MACRONIX International Co., Ltd., Hsinchu, TW;
Abstract
Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.