The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2010
Filed:
Jun. 07, 2005
Dina H. Triyoso, Austin, TX (US);
Olubunmi O. Adetutu, Austin, TX (US);
Hsing H. Tseng, Austin, TX (US);
Dina H. Triyoso, Austin, TX (US);
Olubunmi O. Adetutu, Austin, TX (US);
Hsing H. Tseng, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl, purging the chamber with an inert, pulsing the chamber with an HO or DO, and purging the chamber with an inert.