The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2010
Filed:
Dec. 16, 2003
Zhong-xiang He, Essex Junction, VT (US);
Bradley A. Orner, Cambridge, VT (US);
Vidhya Ramachandran, Ossining, NY (US);
Alvin J. Joseph, Williston, VT (US);
Stephen A. St. Onge, Colchester, VT (US);
Ping-chuan Wang, Hopewell Junction, NY (US);
Zhong-Xiang He, Essex Junction, VT (US);
Bradley A. Orner, Cambridge, VT (US);
Vidhya Ramachandran, Ossining, NY (US);
Alvin J. Joseph, Williston, VT (US);
Stephen A. St. Onge, Colchester, VT (US);
Ping-Chuan Wang, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.