The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
Apr. 18, 2008
OM P. Agrawal, Los Altos, CA (US);
Xiaojie He, Austin, TX (US);
Sajitha Wijesuriya, Macungie, PA (US);
Barry Britton, Orefield, PA (US);
Ming H. Ding, San Jose, CA (US);
Jun Zhao, Allentown, PA (US);
Om P. Agrawal, Los Altos, CA (US);
Xiaojie He, Austin, TX (US);
Sajitha Wijesuriya, Macungie, PA (US);
Barry Britton, Orefield, PA (US);
Ming H. Ding, San Jose, CA (US);
Jun Zhao, Allentown, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In one embodiment, a programmable logic device includes a plurality of programmable logic blocks and a plurality of slices within each of the programmable logic blocks. At least one programmable logic blocks includes a first slice not adapted to provide register functionality or RAM functionality, a second slice adapted to provide register functionality but not RAM functionality, and a third slice adapted to provide register functionality and RAM functionality. Control logic within the programmable logic block is adapted to provide control signals at the programmable block level and at the slice level.