The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
Oct. 24, 2006
Binghua HU, Plano, TX (US);
Howard S. Lee, Plano, TX (US);
Henry L. Edwards, Garland, TX (US);
John Lin, Chelmsford, MA (US);
Vladimir N. Bolkhovsky, Framingham, MA (US);
Binghua Hu, Plano, TX (US);
Howard S. Lee, Plano, TX (US);
Henry L. Edwards, Garland, TX (US);
John Lin, Chelmsford, MA (US);
Vladimir N. Bolkhovsky, Framingham, MA (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A double diffused region (), (), () is formed in a semiconductor substrate or in an epitaxial layer () formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().