The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2010
Filed:
Mar. 13, 2006
Bei Chao Zhang, Singapore, SG;
Chun Hui Low, Johor, MY;
Hong Lim Lee, Penang, MY;
Sang Yee Loong, SG, SG;
Qiang Guo, SG, SG;
Bei Chao Zhang, Singapore, SG;
Chun Hui Low, Johor, MY;
Hong Lim Lee, Penang, MY;
Sang Yee Loong, SG, SG;
Qiang Guo, SG, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.