The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2010
Filed:
Feb. 21, 2006
Dureseti Chidambarrao, Weston, CT (US);
Anda C. Mocuta, LaGrangeville, NY (US);
Dan M. Mocuta, LaGrangeville, NY (US);
Carl Radens, LaGrangeville, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Anda C. Mocuta, LaGrangeville, NY (US);
Dan M. Mocuta, LaGrangeville, NY (US);
Carl Radens, LaGrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.