The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

Jun. 23, 2008
Applicants:

Dureseti Chidambarrao, Weston, CT (US);

Judson R. Holt, Wappingers Falls, NY (US);

Meikei Ieong, Wappingers Falls, NY (US);

Qiqing C. Ouyang, Yorktown Heights, NY (US);

Siddhartha Panda, Beacon, NY (US);

Inventors:

Dureseti Chidambarrao, Weston, CT (US);

Judson R. Holt, Wappingers Falls, NY (US);

Meikei Ieong, Wappingers Falls, NY (US);

Qiqing C. Ouyang, Yorktown Heights, NY (US);

Siddhartha Panda, Beacon, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.


Find Patent Forward Citations

Loading…