The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Dec. 04, 2007
Ching-nan Hsiao, Kaohsiung County, TW;
Pei-ing Lee, Chang-Hua Hsien, TW;
Ming-cheng Chang, Taipei County, TW;
Chung-lin Huang, Tao-Yuan, TW;
Hsi-hua Chang, Taoyuan County, TW;
Chih-hsiang Wu, Taipei County, TW;
Ching-Nan Hsiao, Kaohsiung County, TW;
Pei-Ing Lee, Chang-Hua Hsien, TW;
Ming-Cheng Chang, Taipei County, TW;
Chung-Lin Huang, Tao-Yuan, TW;
Hsi-Hua Chang, Taoyuan County, TW;
Chih-Hsiang Wu, Taipei County, TW;
Nanya Technology Corp., Kueishan, Tao-Yuan Hsien, TW;
Abstract
A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.