The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Mar. 30, 2007
Min Chul Sun, Hwasung-si, KR;
Scott Jansen, East Fishkill, NY (US);
Randy Mann, Poughquag, NY (US);
Oliver D. Patterson, Poughkeepsie, NY (US);
Min Chul Sun, Hwasung-si, KR;
Scott Jansen, East Fishkill, NY (US);
Randy Mann, Poughquag, NY (US);
Oliver D. Patterson, Poughkeepsie, NY (US);
Samsung Electronics Co., Ltd., Suwon-Si, KR;
International Business Machines Corporation, Armonk, NY (US);
Infineon Technologies AG, Neubiberg, DE;
Abstract
Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.