The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2010

Filed:

Dec. 20, 2006
Applicants:

Thai Cheng Chua, Cupertino, CA (US);

Steven Hung, Sunnyvale, CA (US);

Patricia M. Liu, Saratoga, CA (US);

Tatsuya Sato, Cupertino, CA (US);

Alex M. Paterson, San Jose, CA (US);

Valentin Todorov, Fremont, CA (US);

John P. Holland, San Jose, CA (US);

Inventors:

Thai Cheng Chua, Cupertino, CA (US);

Steven Hung, Sunnyvale, CA (US);

Patricia M. Liu, Saratoga, CA (US);

Tatsuya Sato, Cupertino, CA (US);

Alex M. Paterson, San Jose, CA (US);

Valentin Todorov, Fremont, CA (US);

John P. Holland, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/469 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to 'implant' metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material. Embodiments of the invention also provide a cluster tool that is adapted to form a high-k dielectric material, terminate the surface of the high-k dielectric material, perform any desirable post treatment steps, and form the polysilicon and/or metal gate layers.


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