The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Sep. 13, 2006
Harry Chuang, Austin, TX (US);
Mong-song Liang, Hsin-Chu, TW;
Kong-beng Thei, Hsin-Chu, TW;
Jung-hui Kao, Hsin-Chu, TW;
Chung Long Cheng, Hsin-Chu, TW;
Sheng-chen Chung, Hsin-Chu, TW;
Wen-huei Guo, Hsin-Chu, TW;
Harry Chuang, Austin, TX (US);
Mong-Song Liang, Hsin-Chu, TW;
Kong-Beng Thei, Hsin-Chu, TW;
Jung-Hui Kao, Hsin-Chu, TW;
Chung Long Cheng, Hsin-Chu, TW;
Sheng-Chen Chung, Hsin-Chu, TW;
Wen-Huei Guo, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.