The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2010
Filed:
Mar. 24, 2009
OM P. Agrawal, Los Altos, CA (US);
Xiaojie He, Austin, TX (US);
Sajitha Wijesuriya, Macungie, PA (US);
Barry Britton, Orefield, PA (US);
Ming H. Ding, San Jose, CA (US);
Jun Zhao, Allentown, PA (US);
Om P. Agrawal, Los Altos, CA (US);
Xiaojie He, Austin, TX (US);
Sajitha Wijesuriya, Macungie, PA (US);
Barry Britton, Orefield, PA (US);
Ming H. Ding, San Jose, CA (US);
Jun Zhao, Allentown, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In one embodiment of the invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within a programmable logic block. A dual-slice logic block includes a first slice including at least two lookup tables (LUTs); a second slice including at least two LUTs; and a routing circuit coupled to each of the LUTs within the first and second slices. The routing circuit is adapted to share outputs of the dual-slice logic block among the LUTs. In another embodiment of the invention, the dual-slice logic block includes a second routing circuit coupled to each of the LUTs within the first and second slices. The second routing circuit is adapted to share inputs of the dual-slice logic block among the LUTs.