The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Sep. 10, 2007
Shu-huei Lin, Hsinchu, TW;
Chong-gim Gan, Yuanlin Township, Changhuu County, TW;
Yi-hsun Wu, Hsin-Chu, TW;
Yu-chang Lin, Hsinchu, TW;
Shu-Huei Lin, Hsinchu, TW;
Chong-Gim Gan, Yuanlin Township, Changhuu County, TW;
Yi-Hsun Wu, Hsin-Chu, TW;
Yu-Chang Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A system includes a driving device operating at first supply voltage Vand having a CMOS output. A driven devise operates at a second supply voltage Vlower than the first supply voltage V, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail V. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to V. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.