The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Mar. 01, 2004
Errol Todd Ryan, Wappingers Fall, NY (US);
Paul R. Besser, Sunnyvale, CA (US);
Simon Siu-sing Chan, Saratoga, CA (US);
Robert J. Chiu, San Jose, CA (US);
Mehrdad Mahanpour, Union City, CA (US);
Minh Van Ngo, Fremont, CA (US);
Errol Todd Ryan, Wappingers Fall, NY (US);
Paul R. Besser, Sunnyvale, CA (US);
Simon Siu-Sing Chan, Saratoga, CA (US);
Robert J. Chiu, San Jose, CA (US);
Mehrdad Mahanpour, Union City, CA (US);
Minh Van Ngo, Fremont, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.