The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2010
Filed:
Oct. 25, 2006
Manish Pandey, San Jose, CA (US);
Rajat Arora, Sunnyvale, CA (US);
Chih-chang Lin, Saratoga, CA (US);
Huan-chih Tsai, Saratoga, CA (US);
Bharat Chandramouli, San Jose, CA (US);
Kei-yong Khoo, San Jose, CA (US);
Manish Pandey, San Jose, CA (US);
Rajat Arora, Sunnyvale, CA (US);
Chih-Chang Lin, Saratoga, CA (US);
Huan-Chih Tsai, Saratoga, CA (US);
Bharat Chandramouli, San Jose, CA (US);
Kei-Yong Khoo, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.