Using oxynitride spacer to reduce parasitic capacitance in cmos devices

Abstract

A complementary metal oxide semiconductor (CMOS) device has a substrate, a gate structuredisposed atop the substrate, and spacers, deposited on opposite sides of the gate structureto govern formation of deep source drain regions S, D in the substrate. Spacersare formed of an oxynitride (SiONC) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate, forming a gate structureover the substrate, depositing a first layeratop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiONC) layeratop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layeratop the oxynitride layer, and depositing a nitride layerB atop the second layer.