The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2010
Filed:
Jun. 29, 2007
Gauri V. Karve, Fishkill, NY (US);
Cristiano Capasso, Austin, TX (US);
Srikanth B. Samavedam, Fishkill, NY (US);
James K. Schaeffer, Wappingers Falls, NY (US);
William J. Taylor, Jr., Round Rock, TX (US);
Gauri V. Karve, Fishkill, NY (US);
Cristiano Capasso, Austin, TX (US);
Srikanth B. Samavedam, Fishkill, NY (US);
James K. Schaeffer, Wappingers Falls, NY (US);
William J. Taylor, Jr., Round Rock, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.