The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2010

Filed:

May. 02, 2008
Applicants:

Takeshi Sakai, Hitachinaka, JP;

Yasushi Ishii, Mito, JP;

Tsutomu Okazaki, Itami, JP;

Masaru Nakamichi, Hitachinaka, JP;

Toshikazu Matsui, Kodaira, JP;

Kyoya Nitta, Kokubunji, JP;

Satoru Machida, Hitachinaka, JP;

Munekatsu Nakagawa, Hitachinaka, JP;

Yuichi Tsukada, Kodaira, JP;

Inventors:

Takeshi Sakai, Hitachinaka, JP;

Yasushi Ishii, Mito, JP;

Tsutomu Okazaki, Itami, JP;

Masaru Nakamichi, Hitachinaka, JP;

Toshikazu Matsui, Kodaira, JP;

Kyoya Nitta, Kokubunji, JP;

Satoru Machida, Hitachinaka, JP;

Munekatsu Nakagawa, Hitachinaka, JP;

Yuichi Tsukada, Kodaira, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.


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