The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Jan. 24, 2007
Anthony K. Stamper, Williston, VT (US);
Anil K. Chinthakindi, Haymarket, VA (US);
Douglas D. Coolbaugh, Essex Junction, VT (US);
Timothy J. Dalton, Ridgefield, CT (US);
Daniel C. Edelstein, White Plains, NY (US);
Ebenezer E. Eshun, Wappingers Falls, NY (US);
Jeffrey P. Gambino, Westford, VT (US);
William J. Murphy, North Ferrisburgh, VT (US);
Kunal Vaed, Poughkeepsie, NY (US);
Anthony K. Stamper, Williston, VT (US);
Anil K. Chinthakindi, Haymarket, VA (US);
Douglas D. Coolbaugh, Essex Junction, VT (US);
Timothy J. Dalton, Ridgefield, CT (US);
Daniel C. Edelstein, White Plains, NY (US);
Ebenezer E. Eshun, Wappingers Falls, NY (US);
Jeffrey P. Gambino, Westford, VT (US);
William J. Murphy, North Ferrisburgh, VT (US);
Kunal Vaed, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line ('FEOL') devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric ('ILD') layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.