The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Jun. 30, 2005
Stefan Rusu, Sunnyvale, CA (US);
Tsung-yung Chang, Cupertino, CA (US);
Kevin Zhang, Portland, CA (US);
Fatih Hamzaoglu, Hillsboro, OR (US);
Jonathan Shoemaker, Sunnyvale, CA (US);
Ming Huang, San Jose, CA (US);
Stefan Rusu, Sunnyvale, CA (US);
Tsung-Yung Chang, Cupertino, CA (US);
Kevin Zhang, Portland, CA (US);
Fatih Hamzaoglu, Hillsboro, OR (US);
Jonathan Shoemaker, Sunnyvale, CA (US);
Ming Huang, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.