The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7648886 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 19, 2010

Filed:

Jan. 14, 2003
Applicants:

Minh-van Ngo, Fremont, CA (US);

Qi Xiang, San Jose, CA (US);

Paul R. Besser, Sunnyvale, CA (US);

Eric N. Paton, Morgan Hill, CA (US);

Ming-ren Lin, Cupertino, CA (US);

Inventors:

Minh-Van Ngo, Fremont, CA (US);

Qi Xiang, San Jose, CA (US);

Paul R. Besser, Sunnyvale, CA (US);

Eric N. Paton, Morgan Hill, CA (US);

Ming-Ren Lin, Cupertino, CA (US);

Assignee:

Globalfoundries Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.


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Ngo, Minh-Van. (2010). Shallow trench isolation process (U.S. Patent No. 7648886). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7648886

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