The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 2010
Filed:
Aug. 10, 2006
Huajie Chen, Danbury, CT (US);
Dureseti Chidambarrao, Weston, CT (US);
Sang-hyun OH, Santa Barbara, CA (US);
Siddhartha Panda, Beacon, NY (US);
Werner A. Rausch, Stormville, NY (US);
Tsutomu Sato, Poughquag, NY (US);
Henry K. Utomo, Poughkeepsie, NY (US);
Huajie Chen, Danbury, CT (US);
Dureseti Chidambarrao, Weston, CT (US);
Sang-Hyun Oh, Santa Barbara, CA (US);
Siddhartha Panda, Beacon, NY (US);
Werner A. Rausch, Stormville, NY (US);
Tsutomu Sato, Poughquag, NY (US);
Henry K. Utomo, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A field effect transistor ('FET') is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.