The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2010

Filed:

Dec. 26, 2006
Applicants:

Cheng Siew Tay, 11200 Tanjung Bungah, Penang, MY;

Swee Kian Cheng, 09000 Kulim, Kedah, MY;

Eng Huat Goh, Penang, MY;

Inventors:

Cheng Siew Tay, 11200 Tanjung Bungah, Penang, MY;

Swee Kian Cheng, 09000 Kulim, Kedah, MY;

Eng Huat Goh, Penang, MY;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.


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Tay, Cheng. (2010). Method and apparatus for reducing electrical interconnection fatigue (U.S. Patent No. 7642660). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7642660

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