The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2010
Filed:
Jan. 10, 2008
Agni Mitra, Gilbert, AZ (US);
Darrell G. Hill, Tempe, AZ (US);
Karthik Rajagopalan, Chandler, AZ (US);
Adolfo C. Reyes, Tempe, AZ (US);
Agni Mitra, Gilbert, AZ (US);
Darrell G. Hill, Tempe, AZ (US);
Karthik Rajagopalan, Chandler, AZ (US);
Adolfo C. Reyes, Tempe, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.