The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2009
Filed:
Oct. 17, 2005
Dror Hurwitz, Gilboa, IL;
Mardechay Farkash, Haifa, IL;
Eva Igner, Haifa, IL;
Amit Zeidler, Kiryat Tivon, IL;
Boris Statnikov, Nazerth Illit, IL;
Benny Michaeli, Nazareth Illit, IL;
Dror Hurwitz, Gilboa, IL;
Mardechay Farkash, Haifa, IL;
Eva Igner, Haifa, IL;
Amit Zeidler, Kiryat Tivon, IL;
Boris Statnikov, Nazerth Illit, IL;
Benny Michaeli, Nazareth Illit, IL;
Amitec-Advanced Multilayer Interconnect Technologies Ltd., Migdal Harmek, IL;
Abstract
A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto.