The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2009
Filed:
Sep. 26, 2003
Seiji Funaba, Tokyo, JP;
Hisashi Abo, Tokyo, JP;
Takao Ono, Tokyo, JP;
Koji Hosokawa, Tokyo, JP;
Yoji Nishio, Tokyo, JP;
Atsushi Nakamura, Tokyo, JP;
Tomohiko Sato, Tokyo, JP;
Seiji Funaba, Tokyo, JP;
Hisashi Abo, Tokyo, JP;
Takao Ono, Tokyo, JP;
Koji Hosokawa, Tokyo, JP;
Yoji Nishio, Tokyo, JP;
Atsushi Nakamura, Tokyo, JP;
Tomohiko Sato, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Renesas Eastern Japan Semiconductor, Inc., Tokyo, JP;
Abstract
A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.