The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2009
Filed:
Sep. 27, 2006
Harry Chuang, Austin, TX (US);
Kong-beng Thei, Hsinchu, TW;
Chung-long Cheng, Hsinchu, TW;
Sheng-chen Chung, Hsinchu, TW;
Wen-huei Guo, Hsinchu, TW;
Jung-hui Kao, Hsinchu, TW;
Ryan Chia-jen Chen, Chiayi, TW;
Mong-song Liang, Hsinchu, TW;
Harry Chuang, Austin, TX (US);
Kong-Beng Thei, Hsinchu, TW;
Chung-Long Cheng, Hsinchu, TW;
Sheng-Chen Chung, Hsinchu, TW;
Wen-Huei Guo, Hsinchu, TW;
Jung-Hui Kao, Hsinchu, TW;
Ryan Chia-Jen Chen, Chiayi, TW;
Mong-Song Liang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.