The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2009
Filed:
Apr. 25, 2008
Hyung-jin Jeon, Gunpo-si, KR;
Sung Yi, Suwon-si, KR;
Young-do Kweon, Seoul, KR;
Jong-yun Lee, Incheon, KR;
Joon-seok Kang, Suwon-si, KR;
Seung-wook Park, Suwon-si, KR;
Hyung-Jin Jeon, Gunpo-si, KR;
Sung Yi, Suwon-si, KR;
Young-Do Kweon, Seoul, KR;
Jong-Yun Lee, Incheon, KR;
Joon-Seok Kang, Suwon-si, KR;
Seung-Wook Park, Suwon-si, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.